Conductive lines with subtractive cuts

ABSTRACT

Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.

BACKGROUND

The present invention generally relates to integrated chip fabricationand, more particularly, to the fabrication of multi-layer integratedchips with conductive lines.

Patterning interconnects with small dimensions, for example less thanabout 50 nm, can be challenging, with complex hardmask memorizationlayers being used to assemble lines and cuts. Complex hardmask stacksoften involve multiple consecutive layers of different materials,necessitating multiple etches to get through each layer, which canresult in a poor-quality final pattern. Additionally, complex hardmaskstacks increase both cost and processing time, and the increased numberof masks increases the likelihood of mispositioning errors.

SUMMARY

An integrated chip includes a dielectric layer, that includes at leastone trench and at least one plug region. A line is formed in thedielectric layer in the at least one trench and that terminates at theplug region. A dielectric plug is formed in the plug region.

An integrated chip includes a dielectric layer that includes a trenchand two plug regions. A line is formed in the dielectric layer in thetrench between the two plug regions and terminates at the plug regions.Dielectric plugs are formed in the two plug regions.

An integrated chip includes a dielectric layer that includes twotrenches and a plug regions. Lines are formed in the dielectric layer inthe trenches with the plug region between the lines, terminating at theplug region. A dielectric plug is formed in the plug region.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description will provide details of preferred embodimentswith reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a step in the fabrication ofconductive lines in a multi-layer integrated chip using subtractivecuts, showing the formation of a conductive layer on a substrate, inaccordance with an embodiment of the present invention;

FIG. 2 is a cross-sectional view of a step in the fabrication ofconductive lines in a multi-layer integrated chip using subtractivecuts, showing the formation of cuts in the conductive layer thatestablish plug locations for later interruption of conductive lines, inaccordance with an embodiment of the present invention;

FIG. 3 is a top-down view of a step in the fabrication of conductivelines in a multi-layer integrated chip using subtractive cuts, showingthe relative positions of the cuts in the conductive layer, inaccordance with an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a step in the fabrication ofconductive lines in a multi-layer integrated chip using subtractivecuts, showing the formation of dielectric plugs in the cuts in theconductive layer, in accordance with an embodiment of the presentinvention;

FIG. 5 is a cross-sectional view of a step in the fabrication ofconductive lines in a multi-layer integrated chip using subtractivecuts, showing the formation of line pattern mask over the conductivelayer and the dielectric plugs, in accordance with an embodiment of thepresent invention;

FIG. 6 is a top-down view of a step in the fabrication of conductivelines in a multi-layer integrated chip using subtractive cuts, showingthe relative positions of the line pattern mask and the dielectricplugs, in accordance with an embodiment of the present invention;

FIG. 7 is a top-down view of a step in the fabrication of conductivelines in a multi-layer integrated chip using subtractive cuts, showingthe patterning of the conductive layer around the line pattern mask, inaccordance with an embodiment of the present invention;

FIG. 8 is a top-down view of a step in the fabrication of conductivelines in a multi-layer integrated chip using subtractive cuts, showingthe removal of the line pattern mask to expose the underlying conductivelines, in accordance with an embodiment of the present invention;

FIG. 9 is a top-down view of a step in the fabrication of conductivelines in a multi-layer integrated chip using subtractive cuts, showingthe formation of an interlayer dielectric around the conductive linesand the dielectric plugs, in accordance with an embodiment of thepresent invention; and

FIG. 10 is a block/flow diagram of a method of fabricating conductivelines in a multi-layer integrated chip using subtractive cuts inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

Embodiments of the present invention form conductive lines in anintegrated chip by forming cuts before patterning the conductive linesthemselves. This avoids the need for complex hardmask patterns. Openingsare formed in a metal layer and dielectric material is deposited to fillthe openings. When the lines are subsequently patterned, they willterminate at the deposited dielectric fills, with no need for furthercut processes. Additionally, because the interlayer dielectric is thenformed after the lines and the cuts have already been formed, there isno need to perform an anisotropic etch that could potentially damage theinterlayer dielectric. This makes it possible to use materials that areless robust, such as low-k dielectric materials, thereby reducingparasitic capacitances.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1 , a cross-sectional view ofa step in the fabrication of a multi-layer integrated chip is shown. Asubstrate layer 102 is shown. In some embodiments, the substrate layer102 can be formed from, e.g., a dielectric material such as silicondioxide or a glass material. The substrate layer 102 can include activeand/or passive electronic components, such as transistors, capacitors,transmission lines, vias, etc. There can additionally be one or morefurther layers underlying the substrate layer 102, with connectivitybetween the layers being provided by via structures.

A layer of conductive material 104 is formed over the substrate layer102. In embodiments where the substrate layer 102 includes vias to itssurface, the conductive layer 104 will make electrical contact with thevias to provide electrical communication between the layers. Theconductive layer 104 can be formed from any appropriate conductivematerial, for example a metal, such as tungsten, nickel, titanium,molybdenum, tantalum, copper, platinum, silver, gold, ruthenium,iridium, rhenium, rhodium, and alloys thereof. The conductive layer 104can alternatively be formed from a doped semiconductor material such as,e.g., doped polysilicon.

It should be understood that the conductive layer 104 can be formedusing any appropriate deposition process, such as chemical vapordeposition (CVD), physical vapor deposition (PVD), atomic layerdeposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is adeposition process in which a deposited species is formed as a result ofchemical reaction between gaseous reactants at greater than roomtemperature (e.g., from about 25° C. about 900° C.). The solid productof the reaction is deposited on the surface on which a film, coating, orlayer of the solid product is to be formed. Variations of CVD processesinclude, but are not limited to, Atmospheric Pressure CVD (APCVD), LowPressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD(MOCVD) and combinations thereof may also be employed. In alternativeembodiments that use PVD, a sputtering apparatus may includedirect-current diode systems, radio frequency sputtering, magnetronsputtering, or ionized metal plasma sputtering. In alternativeembodiments that use ALD, chemical precursors react with the surface ofa material one at a time to deposit a thin film on the surface. Inalternative embodiments that use GCIB deposition, a high-pressure gas isallowed to expand in a vacuum, subsequently condensing into clusters.The clusters can be ionized and directed onto a surface, providing ahighly anisotropic deposition.

Although it is specifically contemplated that the present embodimentscan be used for the formation of conductive lines, it should beunderstood that the conductive layer 104 can be replaced by anyappropriate non-conducting or semiconducting material to form lines fromany material that is called for. For example, the present embodimentscan be used to form mandrels that can be used for patterning theunderlying substrate layer.

Referring now to FIG. 2 , a cross-sectional view of a step in thefabrication of a multi-layer integrated chip is shown. Openings 202 areformed in the conductive layer 104. The openings 202 can be formed by,e.g., masking the conductive layer 104 with a photolithographic maskthat exposes portions of the top surface of the conductive layer. Aphotolithographic process can, for example, use a beam of light toexpose a portion of a masking material, causing a chemical change inthat material. The material can then be “developed” with a developingagent, causing either the exposed or the unexposed region to be removed,leaving the complementary portion. This creates a structure that definesa pattern for a subsequent etch.

An anisotropic etch, such as a reactive ion etch (RIE) can then be usedto form the openings by selectively removing material in the exposedportions, around the photolithographic mask. The anisotropic etchpenetrates through the conductive layer 104, down to the underlyingsubstrate layer 102, but does not damage the substrate layer 102. Asused herein, the term “selective,” in reference to a material removalprocess, denotes that the rate of material removal for a first materialis greater than the rate of removal for at least another material of thestructure to which the material removal process is being applied.

RIE is a form of plasma etching in which during etching the surface tobe etched is placed on a radio-frequency powered electrode. Moreover,during RIE the surface to be etched takes on a potential thataccelerates the etching species extracted from plasma toward thesurface, in which the chemical etching reaction is taking place in thedirection normal to the surface. Other examples of anisotropic etchingthat can be used at this point of the present invention include ion beametching, plasma etching or laser ablation.

Referring now to FIG. 3 , a top-down view of a step in the fabricationof a multi-layer integrated chip is shown. The positioning of theopenings 202 are shown to provide terminations for the conductive linesthat will be formed later in the process. The substrate layer 104 isshown at the bottoms of the openings, with the conductive layer 104forming an otherwise unbroken layer over the substrate layer 102.

It should be understood that the positioning of the openings 202, shownin FIG. 3 , is intended solely for the purpose of illustration. Theactual positioning of the openings 202 in a practical embodiment will bedictated by the design needs of the application, and may, for example,be based on the particular electrical interconnect needs for connectingstructures to one another in an integrated chip. In this illustrativeembodiment, the openings 202 intersect where two different conductivelines will be positioned.

Referring now to FIG. 4 , a cross-sectional view of a step in thefabrication of a multi-layer integrated chip is shown. Dielectric plugs402 are formed in the openings 202. The plugs 402 can be formed by,e.g., depositing a layer of dielectric material by any appropriatedeposition process, such as CVD, PVD, ALD, or GCIB deposition, and thenpolishing down to expose the top surface of the conductive layer 104using, e.g., a chemical mechanical planarization (CMP) process to removethe dielectric material. The dielectric plugs 402 therefore have aheight that is defined by the height of the conductive layer 104.

CMP is performed using, e.g., a chemical or granular slurry andmechanical force to gradually remove upper layers of the device. Theslurry may be formulated to be unable to dissolve, for example, theconductive material, resulting in the CMP process's inability to proceedany farther than that layer.

Referring now to FIG. 5 , a cross-sectional view of a step in thefabrication of a multi-layer integrated chip is shown. A mask 502 isformed over the conductive layer 104. The mask 502 can be formed by aphotolithographic process, to establish a pattern for lines. Forexample, the mask 502 can be patterned with photolithography to followthe paths that conductive lines will follow in the integrated chip.

Referring now to FIG. 6 , a top-down view of a step in the fabricationof a multi-layer integrated chip is shown. This view shows the masks 502being formed across the dielectric plugs 402, establishing line regionsthat run between the dielectric plugs 202. In at least some embodiments,it is contemplated that the line pattern mask 502 will extend over adielectric plug 202, crossing from one side to the other. It should beunderstood that the line pattern masks need not terminate at adielectric plug 202, but can instead terminate at an open end. Thedielectric plugs 402 separate a single line region, defined by the linepattern mask 502, into two or more distinct line regions.

Referring now to FIG. 7 , a top-down view of a step in the fabricationof a multi-layer integrated chip is shown. A selective anisotropic etchis used to remove the exposed portions of the conductive layer 104,exposing the underlying substrate layer 102. The portions of theconductive layer 104 that are protected by the mask 502 form conductivelines, which terminate at the dielectric plugs 402.

Referring now to FIG. 8 , a top-down view of a step in the fabricationof a multi-layer integrated chip is shown. The mask 502 is etched awayby any appropriately selective isotropic or anisotropic etch process,exposing the underlying conductive lines 802. Because the line patternmask 502 was positioned across the dielectric plugs 402, the conductivelines intersect with, and terminate at, the dielectric plugs 402.

Referring now to FIG. 9 , a top-down view of a step in the fabricationof a multi-layer integrated chip is shown. A layer of dielectricmaterial is filled in around the conductive lines 802 and the dielectricplugs 402. The dielectric material can be formed by any appropriatedeposition process to cover the top surface of the conductive lines 802,and can then be polished back to expose the conductive lines 802 using,e.g., a CMP process that stops on the conductive material, to form theinterlayer dielectric 902.

In some embodiments, the dielectric plugs 402 can be etched away, usingany appropriately selective isotropic or anisotropic etch, beforeforming the interlayer dielectric 902. In such embodiments, theinterlayer dielectric 902 fills the spaces between ends of theconductive lines 802.

It is specifically contemplated that the interlayer dielectric 902 canbe formed form ultra-low-k dielectric material to minimize parasiticcapacitance. As used herein, the term “low-k” refers to a material thathas a dielectric constant k that is lower than the dielectric constantof silicon dioxide. The term “ultra-low-k” refers to a material that hasa dielectric constant substantially lower than that of silicon dioxide.An exemplary low-k dielectric material is SiCOH, with a dielectricconstant between about 2.7 and about 3.0. An exemplary ultra-low-kdielectric material is octamethylcyclotetrasiloxane, with a dielectricconstant of about 2.7.

An advantage of forming the interlayer dielectric 902 after the cutlines 802 are formed can be that the interlayer dielectric does notinclude any damage from the etches that would otherwise be used to formthe cuts. In particular, although anisotropic etches can be madeselective to the material that is being removed, such selectivity israrely perfect. As a result, neighboring materials can be damaged duringthe etch. The present embodiments avoid this by forming structures thatinterrupt the lines, before the interlayer dielectric 902 is everdeposited.

It is to be understood that aspects of the present invention will bedescribed in terms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps can be varied within the scope of aspects of the presentinvention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements can also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements can be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

The present embodiments can include a design for an integrated circuitchip, which can be created in a graphical computer programming language,and stored in a computer storage medium (such as a disk, tape, physicalhard drive, or virtual hard drive such as in a storage access network).If the designer does not fabricate chips or the photolithographic masksused to fabricate chips, the designer can transmit the resulting designby physical means (e.g., by providing a copy of the storage mediumstoring the design) or electronically (e.g., through the Internet) tosuch entities, directly or indirectly. The stored design is thenconverted into the appropriate format (e.g., GDSII) for the fabricationof photolithographic masks, which typically include multiple copies ofthe chip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein can be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case, the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

It should also be understood that material compounds will be describedin terms of listed elements, e.g., SiGe. These compounds includedifferent proportions of the elements within the compound, e.g., SiGeincludes Si_(x)Ge_(1-x) where x is less than or equal to 1, etc. Inaddition, other elements can be included in the compound and stillfunction in accordance with the present principles. The compounds withadditional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment”,as well as other variations thereof, means that a particular feature,structure, characteristic, and so forth described in connection with theembodiment is included in at least one embodiment. Thus, the appearancesof the phrase “in one embodiment” or “in an embodiment”, as well anyother variations, appearing in various places throughout thespecification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This can be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, can be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the FIGS. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the FIGS. For example, if the device in theFIGS. is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device can be otherwise oriented (rotated 90degrees or at other orientations), and the spatially relativedescriptors used herein can be interpreted accordingly. In addition, itwill also be understood that when a layer is referred to as being“between” two layers, it can be the only layer between the two layers,or one or more intervening layers can also be present.

It will be understood that, although the terms first, second, etc. canbe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, a first element discussed belowcould be termed a second element without departing from the scope of thepresent concept.

Referring now to FIG. 10 , a method for forming conductive lines in amulti-layer integrated chip is shown. Block 1002 forms a conductivelayer 104 on a substrate layer 102 using any appropriate depositionprocess. Block 1004 forms a cut mask over the conductive layer using anyappropriate deposition process followed by, e.g., an appropriatephotolithograph etching process. Block 1006 uses an anisotropic etch toform openings 202 in the conductive layer 104, by removing the materialthat is exposed by the cut mask. Block 1008 then etches away the cutmask by any appropriate isotropic or anisotropic etch.

Block 1010 forms the dielectric plugs 402 in the openings 202. Block1010 deposits dielectric material by any appropriate deposition processand then polished any excess dielectric material away using, e.g., a CMPprocess that stops on the conductive layer 104.

Block 1012 forms a line mask 502 on the conductive layer 104, using anyappropriate photolithographic process, to define a line region. Block1014 etches down into the conductive layer 104, using an anisotropicetch, to expose the underlying substrate layer 102. Block 1016 thenremoves the line mask 502, exposing the underlying conductive lines 802,which are cut by dielectric plugs 402. Block 1018 forms interlayerdielectric 902 around the conductive lines 402 by depositing anappropriate dielectric material and polishing the dielectric materialdown to the height of the conductive lines 802 using a CMP process. Insome embodiments, block 1018 can first etch away the dielectric plugs202 before forming the interlayer dielectric 802, such that theinterlayer dielectric material is filled in the cut regions betweenconductive lines 802.

Having described preferred embodiments of conductive lines withsubtractive cuts (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments disclosed which are within the scope of the invention asoutlined by the appended claims. Having thus described aspects of theinvention, with the details and particularity required by the patentlaws, what is claimed and desired protected by Letters Patent is setforth in the appended claims.

What is claimed is:
 1. An integrated chip, comprising: a dielectriclayer, that includes at least one trench and at least one plug region; aline, formed in the dielectric layer in the at least one trench, thatterminates at the plug region; and a dielectric plug formed in the plugregion.
 2. The integrated chip of claim 1, wherein the dielectric layeris formed from an ultra-low-k dielectric material.
 3. The integratedchip of claim 2, wherein the dielectric layer is formed fromoctamethylcyclotetrasiloxane.
 4. The integrated chip of claim 1, whereinthe line is formed from a conductive material.
 5. The integrated chip ofclaim 1, wherein the line is narrower than the dielectric plug.
 6. Theintegrated chip of claim 1, wherein the top surface of the dielectriclayer is not damaged by any anisotropic etch.
 7. The integrated chip ofclaim 1, further comprising a second line on a side of the dielectricplug that is opposite to the line.
 8. The integrated chip of claim 1,further comprising a second dielectric plug on a side of the conductiveline that is opposite to the dielectric plug.
 9. The integrated chip ofclaim 1, wherein the line is in direct contact with a sidewall of thedielectric plug.
 10. An integrated chip, comprising: a dielectric layer,that includes a trench and two plug regions; a line, formed in thedielectric layer in the trench between the two plug regions, thatterminates at the plug regions; and dielectric plugs formed in the twoplug regions.
 11. The integrated chip of claim 10, wherein thedielectric layer is formed from octamethylcyclotetrasiloxane.
 12. Theintegrated chip of claim 10, wherein the line is formed from aconductive material.
 13. The integrated chip of claim 12, wherein theline is narrower than the dielectric plugs.
 14. The integrated chip ofclaim 10, wherein the top surface of the dielectric layer is not damagedby any anisotropic etch.
 15. The integrated chip of claim 10, whereinthe line is in direct contact with sidewalls of the dielectric plugs.16. An integrated chip, comprising: a dielectric layer, that includestwo trenches and a plug regions; lines, formed in the dielectric layerin the trenches with the plug region between the lines, terminating atthe plug region; and a dielectric plug formed in the plug region. 17.The integrated chip of claim 16, wherein the dielectric layer is formedfrom octamethylcyclotetrasiloxane.
 18. The integrated chip of claim 16,wherein the lines are formed from a conductive material.
 19. Theintegrated chip of claim 16, wherein the line is narrower than thedielectric plugs.
 20. The integrated chip of claim 16, wherein the topsurface of the dielectric layer is not damaged by any anisotropic etch.